1. Technical Field
The present disclosure relates to the field of semiconductors, and more particularly to an image sensor device and a method of manufacturing the same.
2. Description of the Related Art
Advanced packaging solutions, for example through-silicon via (TSV) process technology, have been implemented for complementary metal-oxide-semiconductor (CMOS) image sensors (the CMOS image sensors abbreviated herein as “CIS”). A CIS built using TSV process technology is typically formed on a wafer level chip scale package (WLCSP), which offers cost savings and form factor advantages over a conventional chip on board (COB) package.
As TSV process technology continues to develop, WLCSP is being applied during and post-TSV processing, and TSV dimensions are being reduced, so as to meet the requirements of high-end CIS products. TSV dimensions may include, for example, dimensions of the pads for interconnecting the TSVs.
In a CIS WLCSP, a height of the TSV (as measured from a top pad to a bottom package bump) depends on a depth of the through via (typically less than 300 μm). As a result, the silicon wafer (in which the TSV is formed) has to undergo backside thinning to reduce the thickness of the wafer to less than 300 μm. The silicon wafer is typically mounted (bonded) to a supporting substrate prior to thinning.
After the silicon wafer has been mounted to the supporting substrate, the bonded structure undergoes TSV processing steps including backgrinding, etching, formation of isolation structures, etc. Good bonding quality is necessary to minimize the stresses exerted on the bonded structure during TSV processing.